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july 2010 doc id 17709 rev 2 1/33 1 st8024l smartcard interface features designed to be compatible with the nds conditional access system ic card interface 3 v or 5 v supply for the ic (v dd and gnd) three specifically protected half-duplex bi- directional buffered i/o lines to card contacts c4, c7 and c8 step-up converter for v cc generation separately powered from a 5 v 20% supply (v ddp and pgnd) 1.8 v 6.5%, 3 v or 5 v 5% regulated card supply voltage (v cc ) with appropriate decoupling has the fo llowing capabilities: ?i cc < 80 ma at v ddp = 4.75 to 6.5 v ? handles current spikes of 40 na up to 20 mhz ? controls rise and fall times ? filtered overload detection at ~120 ma thermal and short-circuit protection on all card contacts automatic activation and deactivation sequences; initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, v dd or v ddp drop-out enhanced esd-protection on card side (>6 kv) 26 mhz integrated crystal oscillator built-in debounce on card presence contacts one multiplexed status signal off non-inverted control of rst via pin rstin clock generation for cards up to 20 mhz (divided by 1, 2, 4 or 8 through clkdiv1 and clkdiv2 signals) with synchronous frequency changes iso 7816, gsm11.11 and emv 4.0 (payment systems) compatibility supply supervisor for spike-killing during power-on and power-off and power-on reset (threshold fixed internally or externally by a resistor bridge) applications smartcard readers for set-top box ic card readers for banking identification pay tv description the st8024l is a complete low-cost analog interface for asynchronous class a, b and c smartcards. it can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. st8024lcdr and ST8024LCTR are compatible with st8024 (with the exception of v th(ext)rise/fall ). so-28 tssop-28 tssop-20 table 1. device summary order code poradj/1.8v function temperature range package packaging st8024lcdr poradj ?25 to 85 c so-28 (tape and reel) 1000 parts per reel ST8024LCTR poradj ?25 to 85 c tssop-28 (tape and reel) 2500 parts per reel st8024lacdr 1.8 v ?25 to 85 c so-28 (tape and reel) 1000 parts per reel st8024ltr 1.8 v ?25 to 85 c tssop-20 (tape and reel) 2500 parts per reel www.st.com
contents st8024l 2/33 doc id 17709 rev 2 contents 1 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 without external divider on pin poradj . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 with an external divider on pin poradj . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.3 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 clock circuitry (only on so-28 and tssop-28 packages) . . . . . . . . . . . . 17 5.4 i/o transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9 vcc generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10 fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.11 v cc selection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
st8024l list of tables doc id 17709 rev 2 3/33 list of tables table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. electrical characteristics over recommended operating condition . . . . . . . . . . . . . . . . . . . . 9 table 7. step-up converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. card supply voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. crystal connection (pins xtal1 and xtal2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. data lines (pins i/o, i/ouc, aux1, aux2, aux1uc and aux2uc). . . . . . . . . . . . . . . . . 11 table 11. data lines to card reader (pins i/o, aux1 and aux2 with integrated 11 k pull-up resistor to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 12. data lines to microcontroller (pins i/ouc, aux1uc and aux2uc with integrated 11 k pull-up resistor to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 13. internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 14. reset output to card reader (pin rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 15. clock output to card reader (pin clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 16. control inputs (pin s clkdiv1, clkdiv2, cmdvcc , rstin, 5v/3v and poradj/1.8v) . 14 table 17. card presence inputs (pins pres and pres ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 18. interrupt output (pin off nmos drain with integrated 20 k pull-up resistor to v dd ) . . . . 14 table 19. protection and limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 20. timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 21. clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 22. card presence indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 23. v cc selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 24. so-28 small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 25. tssop-20 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 26. tssop-28 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 27. so-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. tssop-20 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 29. tssop-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of figures st8024l 4/33 doc id 17709 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. definition of output and input transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 4. voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. activation sequence using rstin and cmdvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. activation sequence at t 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. behavior of off , cmdvcc , pres and v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. so-28 small outline, package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. tssop-20 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. tssop-28 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. so-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. tssop-20 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 16. tssop-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
st8024l diagram doc id 17709 rev 2 5/33 1 diagram figure 1. block diagram 1. to be used with the poradj pin if needed 2. not available in the tssop-20l package c s 1 8 100 s t 8 024l c1? c1+ 1 8 poradj/1. 8 v s equencer o s cillator clock circuitry clk hor s eq thermal protection clock buffer i/o tran s ceiver i/o tran s ceiver i/o tran s ceiver r s t buffer v cc generator internal o s cillator 2.5 mhz s tep-up converter alarm power_on en1 clkup en2 pv cc en5 en4 en 3 voltage s en s e internal reference s upply 21 6 7 5 100nf 100nf v ddp 100nf v dd 2 3 20 19 3 1 2 clkdiv2 (2) clkdiv2 (1) 5v/ 3 v cmdvcc r s tin off v dd v ref r 2 (1) r 1 (1) xtal1 xtal2 (2) 24 25 27 2 8 26 22 aux1uc (2) aux2uc (2) i/ouc gnd 4 8 v up pgnd 100nf v cc 100nf cgnd r s t clk pre s pre s (2) aux1 (2) aux2 (2) i/o 17 14 16 15 10 9 1 3 12 11
pin configuration st8024l 6/33 doc id 17709 rev 2 2 pin configuration figure 2. pin connections s o-2 8 /t ss op-2 8 t ss op-20 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 5v/ 3 v pgnd c1+ v ddp c1? v up pre s cgnd i/o clk r s t v cc 1. 8 v cmdvcc r s tin v dd gnd off 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 xtal1 i/ouc clkdiv1 clkdiv2 5v/ 3 v pgnd c1+ v ddp c1? v up pre s pre s i/o aux2 aux1 cgnd clk r s t v cc poradj cmdvcc r s tin v dd gnd off xtal1 xtal2 i/ouc aux1uc aux2uc am04929v1 s o-2 8 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 clkdiv1 clkdiv2 5v/ 3 v pgnd c1+ v ddp c1? v up pre s pre s i/o aux2 aux1 cgnd clk r s t v cc 1. 8 v cmdvcc r s tin v dd gnd off xtal1 xtal2 i/ouc aux1uc aux2uc s t 8 024lcdr s t 8 024lctr s t 8 024lacdr s t 8 024ltr table 2. pin description symbol name and function so-28/ tssop-28 tssop-20 clkdiv1 control of clk frequency (internal 11 k pull-up resistor connected to v dd ) 1n.a clkdiv2 control of clk frequency (internal 11 k pull-down resistor connected to v dd ) 2n.a 5v/3v 5 v or 3 v v cc selection for communication with the smartcard. logic high selects 5 v operation and logic low selects 3 v operation. if the 1.8v pin is logic high, the 5v/3v pin is a ?don't care? (see ta bl e 2 4 for a description of the v cc selection settings.) 31 pgnd power ground for step-up converter 4 2 c1+ external cap. step-up converter 5 3 v ddp power supply for step-up converter 6 4 c1? external cap. step-up converter 7 5 v up output of step-up converter 8 6 pres card presence input (active low) - bonding option 9 n.a pres card presence input (active high) 10 7
st8024l pin configuration doc id 17709 rev 2 7/33 i/o data line to and from card (c7) (internal 11 k pull-up resistor connected to v cc ) 11 8 aux2 auxiliary line to and from card (c8) (internal 11 k pull-up resistor connected to v cc ) 12 n.a. aux1 auxiliary line to and from card (c4) (internal 11 k pull-up resistor to v cc )13 n.a cgnd ground for card signal (c5) 14 9 clk clock to card (c3) 15 10 rst card reset (c2) 16 11 v cc supply voltage for the card (c1) 17 12 poradj power-on reset threshold adjustment input 18 n.a. 1.8v 1.8 v v cc operation selection. logic high selects 1.8 v operation and overrides any setting on the 5v/3v pin. 18/n.a. (1) 13 cmdvcc start activation sequence input (active low) 19 14 rstin card reset input from mcu 20 15 v dd supply voltage 21 16 gnd ground 22 17 off interrupt to mcu (active low) 23 18 xtal1 crystal or external clock input 24 19 xtal2 crystal connection (leave this pin open if external clock is used) 25 n.a i/ouc mcu data i/o line (internal 11 k pull-up resistor connected to v dd )2620 aux1uc non-inverting receiver input (internal 11 k pull-up resistor connected to v dd ) 27 n.a. aux2uc non-inverting receiver input (internal 11 k pull-up resistor connected to v dd ) 28 n.a. 1. only available on the so-8 package. table 2. pin description (continued) symbol name and function so-28/ tssop-28 tssop-20
maximum ratings st8024l 8/33 doc id 17709 rev 2 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. note: 1 all card contacts are protected against any short with any other card contact. 2 method 3015 (hbm, 1500 , 100 pf) 3 positive pulses and 3 negative pulses on each pin referenced to ground. table 3. absolute maximum ratings symbol parameter min max unit v dd, v ddp supply voltage -0.3 7 v v n1 voltage on pins xtal1, xtal2, 5v/3v , rstin, aux2uc, aux1uc, i/ouc, clkdiv1, clkdiv2, poradj/1.8v, cmdvcc , pres , pres and off -0.3 v dd + 0.3 v v n2 voltage on card contact pins i/o, rst, aux1, aux2 and clk -0.3 v cc + 0.3 v v n3 voltage on pins v up , c1+, c1? 7 v esd1 mil-std-883 class 3 on card contact pins, pres and pres ( note 1 , note 2 ) -6 6 kv esd2 mil-std-883 class 2 on c contac t pins and rstin (note 1, 2) -2 2 kv t j(max) maximum operating junction temperature 150 c t stg storage temperature range -40 150 c table 4. thermal data symbol parameter condition so-28 tssop-20 tssop-28 unit r thja thermal resistance junction-ambient temperature multilayer test board (jedec standard) 56 50 k/w table 5. recommended operating conditions symbol parameter test conditions min. typ. max. unit t a temperature range ?25 85 c
st8024l electrical characteristics doc id 17709 rev 2 9/33 4 electrical characteristics table 6. electrical characteristics over recommended operating condition symbol parameter (1) test conditions min. typ. max. unit v dd supply voltage 2.7 6.5 v v ddp supply voltage for the step-up converter v cc = 5 v; |i cc | < 80 ma for nds application 4.0 5 6.5 v v cc = 5 v; |i cc | < 20 ma 3.0 6.5 v cc = 3 v; |i cc | < 20 ma 2.7 6.5 v v cc = 1.8 v; |i cc | < 20 ma 2.7 6.5 i dd supply current card inactive 1.2 ma card active; f clk = f xtal ; c l = 30 pf 1.5 i ddp step-up converter supply current inactive mode 0.1 ma active mode; f clk = f xtal ; c l = 30 pf; |i cc | = 0 10 v cc = 5 v; |i cc | = 80 ma 50 200 v cc = 3 v; |i cc | = 65 ma 50 100 v cc = 1.8 v; |i cc | = 45 ma 30 60 v th2 falling threshold voltage on v dd no external resistors at pin poradj; v dd level falling 2.35 2.45 2.55 v v hys2 hysteresis of threshold voltage v th2 no external resistors at pin poradj 50 100 150 mv v th(ext)rise external rising threshold voltage on v dd external resistor bridge at pin poradj; v dd level rising 1.17 1.20 1.23 v v th(ext)fall external falling threshold voltage on v dd external resistor bridge at pin poradj; v dd level falling 1.11 1.14 1.17 v v hys(ext) hysteresis of threshold voltage v th(ext) external resistor bridge at pin poradj 30 60 90 mv v hys(ext) hysteresis of threshold voltage v th(ext) variation with temperature external resistor bridge at pin poradj 0.25 mv/k t w width of internal power- on reset pulse no external resistor bridge at pin poradj 4 8 12 ms external resistor bridge at pin poradj 8 16 24 i l leakage current on pin poradj v poradj < 0.5 v ?0.1 4 10 a v poradj > 1.0 v ?1 1 p tot total power dissipation continuous operation; t a = ?25 to 85 c 0.56 w 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c.
electrical characteristics st8024l 10/33 doc id 17709 rev 2 table 7. step-up converter symbol parameter (1) test conditions min. typ. max. unit f clk clock frequency card active 2.2 3.2 mhz v th(vd-vf) threshold voltage for step- up converter to change to voltage follower 5 v card 5.2 5.8 6.2 v 3 v card 3.8 4.1 4.4 1.8 v card 3.8 4.1 4.4 v up output voltage on pin v up (average value) 5 v card 5.2 5.7 6.2 v 3 v card 3.5 3.9 4.3 1.8 v card 3.5 3.9 4.3 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. table 8. card supply voltage characteristics symbol parameter (1) test conditions min. typ. max. unit c vcc external capacitance on pin v cc note 2 and note 3 80 400 nf v cc card supply voltage (including ripple voltage) card inactive; |i cc | = 0 ma 5 v, 3 v and 1.8 v card -0.1 0 0.1 v card inactive; |i cc | = 1 ma 5 v, 3 v and 1.8 v card -0.1 0 0.3 card active; |i cc | < 80 ma 5 v card 4.75 5 5.25 card active; |i cc | < 65 ma 3 v card 2.85 3 3.15 card active; |i cc | < 45 ma 1.8 v card 1.68 1.8 1.92 card active; single current pulse i p = ?100 ma; t p = 2 s 5 v card 4.65 5 5.25 card active; single current pulse i p = ?100 ma; t p = 2 s 3 v card 2.76 3 3.20 card active; single current pulse i p = ?100 ma; t p = 2 s 1.8 v card 1.62 1.8 1.98 card active; current pulses, q p = 40 nas 5 v card 4.65 5 5.25 3 v card 2.76 3 3.20 1.8 v card 1.62 1.8 1.98 card active; current pulses q p = 40 nas with |i cc | < 200 ma, t p < 400 ns 5 v card 4.65 5 5.25 3 v card 2.76 3 3.20 1.8 v card 1.62 1.8 1.98 v cc (ripple) (p-p) ripple voltage on v cc (peak-to-peak value) f ripple = 20 khz to 200 mhz 350 mv
st8024l electrical characteristics doc id 17709 rev 2 11/33 |i cc | card supply current v cc = 0 to 5 v 80 ma v cc = 0 to 3 v 65 v cc = 0 to 1.8 v 55 v cc short circuit to gnd 100 120 150 s r slew rate slew up or down, v cc = 5 v; 3 v; 1.8 v; |i cc | < 30 ma 0.08 0.15 0.22 v/s 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. note 1 table 8. card supply voltage characteristics (continued) symbol parameter (1) test conditions min. typ. max. unit table 9. crystal connection (pins xtal1 and xtal2) symbol parameter (1) test conditions min. typ. max. unit c xtal1,2 external capacitance on pins xtal1, xtal2 depends on type of crystal or resonator used -15pf f xtal crystal frequency 2 - 26 mhz f xtal1 frequency applied on pin xtal1 0-26mhz v ih high level input voltage on pin xtal1 0.7 v dd -v dd +0.3 v v il low level input voltage on pin xtal1 -0.3 - +0.3v dd v 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. table 10. data lines (pins i/o, i/ ouc, aux1, aux2, aux1uc and aux2uc) symbol parameter (1) test conditions min. typ. max. unit t d(i/o-i/ouc), t d(i/ouc-i/o) i/o to i/ouc, i/ouc to i/o falling edge delay --200ns t pu active pull-up pulse width - - 100 ns f i/o(max) maximum frequency on data lines - - 1 mhz c i input capacitance on data lines - - 10 pf 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c.
electrical characteristics st8024l 12/33 doc id 17709 rev 2 table 11. data lines to card reader (pins i/o, aux1 and aux2 with integrated 11 k pull-up resistor to v cc symbol parameter (1) test conditions min. typ. max. unit v o(inactive) output voltage inactive mode no load 0 0.1 v i o(inactive) =1 ma 0.3 i o(inactive) output current inactive mode; pin grounded -1 ma v oh high level output voltage no dc load 0.9 v cc v cc +0.1 v 5 v and 3 v cards; i oh < ?40 a 0.75 v cc v cc +0.1 1.8 v card i oh < ?40 a 0.75 v cc |i oh | 10 ma 0 0.4 v ol low level output voltage i ol = 1 ma 0 0.2 v i ol 15 ma v cc ?0.4 v cc v ih high level input voltage 5 v and 3 v cards 1.5 v cc +0.3 v 1.8 v card 0.6 v cc v il low level input voltage 5 v and 3 v cards 0.3 1.0 v 1.8 v card 0 0.2 |i lih | high level input leakage current v ih = v cc 10 a |i il | low level input current v il = 0 v 600 a r pu integrated pull-up resistor pull-up resistor to v cc 91113k t t(di) data input transition time v il max to v ih min 1.2 s t t(do) data output transition time v o = 0 to v cc ; c l 80 pf; 10% to 90% 0.1 s i pu current when pull-up active v oh = 0.9v cc ; c l = 80 pf -2 ma 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c.
st8024l electrical characteristics doc id 17709 rev 2 13/33 table 12. data lines to microcontroller (pins i/ouc, aux1uc and aux2uc with integrated 11 k pull-up resistor to v dd symbol parameter (1) test conditions min. typ. max. unit v oh high level output voltage 5 v, 3 v and 1.8 v cards; i oh < ?40 a 0.75 v dd v dd +0.1 v no dc load 0.9 v dd v dd +0.1 v ol low level output voltage i ol = 1 ma 0 0.3 v v ih high level input voltage 0.7 v dd v dd +0.3 v v il low level input voltage -0.3 0.3 v dd v |i lih | high level input leakage current v ih = v dd 10 a |i l | low level input current v il = 0 v 600 a r pu internal pull-up resistance to v dd pull-up resistor to v dd 91113k t t(di) data input transition time v il(max) to v ih(min) 1.2 s t t(do) data output transition time v o = 0 to v dd ; c l < 30 pf; 10% to 90% 0.1 s i pu current when pull-up active v oh = 0.9v dd ; c l = 30 pf -1 ma 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. table 13. internal oscillator symbol parameter (1) test conditions min. typ. max. unit f osc(int) frequency of internal oscillator inactive mode 55 140 200 khz active mode 2.2 2.7 3.2 mhz 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted.typical values are at t a = 25 c. table 14. reset output to card reader (pin rst) symbol parameter (1) test conditions min. typ. max. unit v o(inactive) output voltage in inactive mode i o(inactive) = 1 ma 0 - 0.3 v no load 0 - 0.1 i o(inactive) output current inactive mode; pin grounded 0 - -1 ma t d(rstin-rst) rstn to rst delay rst enable - 2 s v ol low level output voltage i ol = 200 a 0 - 0.2 v i ol = 20 ma (current limit) v cc -0.4 - v cc v oh high level output voltage i oh = ?200 a 0.9v cc -v cc v i oh = ?20 ma (current limit) 0 - 0.4 t r, t f rise and fall time c l = 100 pf - 0.1 s 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c.
electrical characteristics st8024l 14/33 doc id 17709 rev 2 table 15. clock output to card reader (pin clk) symbol parameter (1) test conditions min. typ. max. unit v o(inactive) output voltage in inactive mode i o(inactive) = 1 ma 0 - 0.3 v no load 0 - 0.1 i o(inactive) output current clk inactive mode; pin grounded 0-?1ma v ol low level output voltage i ol = 200 a 0 - 0.3 v i ol = 70 ma (current limit) v cc -0.4 - v cc v oh high level output voltage i oh = ?200 a 0.9v cc -v cc v i oh = ?70 ma (current limit) 0 - 0.4 t r, t f rise and fall time c l = 30 pf ( note 4 )-16ns duty factor (except for f xtals )c l = 30 pf ( note 4 )45-55% s r slew rate slew up or down; c l = 30 pf 0.2 - v/ns 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. table 16. control inputs (pin s clkdiv1, clkdiv2, cmdvcc , rstin, 5v/3v and poradj/1.8v) symbol parameter (1) test conditions min. typ. max. unit v il input voltage low ?0.3 0.3v dd v v ih input voltage high 0.7v dd v dd v |i lih | input leakage current high v ih = v dd 1a |i lil | input leakage current low v il = 0 1 a 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. ( note 5 ) table 17. card presence inputs (pins pres and pres ) symbol parameter (1) test conditions min. typ. max. unit v il input voltage low -0.3 - 0.3 v dd v v ih input voltage high 0.7 v dd -v dd +0.3 v |i lih | input leakage current high v ih = v dd -5a |i lil | input leakage current low v il = 0 - 5 a 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. ( note 6 ) table 18. interrupt output (pin off nmos drain with integrated 20 k pull-up resistor to v dd ) symbol parameter (1) test conditions min. typ. max. unit v ol low level output voltage i ol = 2 ma 0 0.3 v v oh high level output voltage i oh = ?15 a 0.75 v dd v r pu integrated pull-up resistor 20 k pull-up resistor to v dd 16 20 24 k 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c.
st8024l electrical characteristics doc id 17709 rev 2 15/33 note: 1 all parameters remain within limits but are tested only statistically for the temperature range. when a parameter is specified as a function of v dd or v cc it means their actual value at the moment of measurement. 2 to meet these specifications, pin v cc should be decoupled to cgnd using two ceramic multilayer capacitors of low esr both with values of 100 nf and 100 nf (see figure 10 ). 3 permitted capacitor values are 100 + 100 nf, or 220 nf. 4 transition time and duty factor definitions are shown in figure 3 ; = t 1 /(t 1 + t 2 ). 5 pin cmdvcc is active low; pin rstin is active high; for clkdiv1 and clkdiv2 functions (see ta b l e 2 0 ). 6 pin pres is active low; pin pres is active high see figure 8 and figure 9 ; pres has an integrated 1.25 a current source to gnd. (pres to v dd ); the card is considered present if at least one of the inputs pres or pres is active. figure 3. definition of output and input transition times table 19. protection and limitation symbol parameter (1) test conditions min. typ. max. unit |i cc(sd) | shutdown and limitation current pin v cc 100 120 150 ma i i/o(lim) limitation current pins i/o, aux1 and aux2 ?15 15 ma i clk(lim) limitation current pin clk ?70 70 ma i rst(lim) limitation current pin rst ?20 20 ma t sd shutdown temperature 150 c 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. table 20. timing symbol parameter (1) test conditions min. typ. max. unit t act activation time (see figure 5 ) for v cc = 5 v 50 220 s t de deactivation time (see figure 7 )5080100s t 3 start of the window for sending clk to card (see figure 6 )130s t 5 end of the window for sending clk to card (see figure 6 )140 s t debounce debounce time pins pres and pres (see figure 8 )140 s 1. v dd = 3.3 v, v ddp = 5 v, f xtal = 10 mhz, unless otherwise noted. typical values are at t a = 25 c. c s 1 3 450
functional description st8024l 16/33 doc id 17709 rev 2 5 functional description throughout this doc ument it is assumed that the reader is familiar with iso7816 terminology. 5.1 power supply the supply pins for the ic are v dd and gnd. v dd should be in the range of 2.7 to 6.5 v. all signals interfacing with the system controller are referred to v dd , therefore v dd should also supply the system controller. all card reader contacts remain inactive during power-on or power-off. the internal circuits are maintained in the reset state until v dd reaches v th2 +v hys2 and for the duration of the internal power-on reset pulse, t w (see figure 4 ). when v dd falls below v th2 , an automatic deactivation of the contacts is performed. a step-up converter is incorporated to generate the 1.8 v (for those devices with the 1.8v pin), 3 v or 5 v card supply voltage (v cc ). the step-up converter should be supplied separately by v ddp and pgnd. due to the possibility of large transient curr ents, the two 100 nf capacitors of the step-up converter should be located as near as possible to the ic and have an esr less than 100 m . supply voltages v dd and v ddp may be applied to the ic in any sequence. after powering the device, off remains low until cmdvcc is set high. during power-off, off falls low when v dd is below the falling threshold voltage. 5.2 voltage supervisor 5.2.1 without external divider on pin poradj the voltage supervisor surveys the v dd supply. a defined reset pulse of approximately 8 ms (t w ) is used internally to keep the ic inactive during power-on or power-off of the v dd supply (see figure 4 ). as long as v dd is less than v th2 + v hys2 , the ic remains inactive whatever the levels on the command lines. this state also lasts for the duration of t w after v dd has reached a level higher than v th2 + v hys2 . when v dd falls below v th2 , a deactivation sequence of the contacts is performed. figure 4. voltage supervisor c s 17790
st8024l functional description doc id 17709 rev 2 17/33 5.2.2 with an external divider on pin poradj if an external resistor bridge is conn ected to pin poradj (r1 and r2 in figure 1 ), then the following occurs: - the internal threshold voltage v th2 is overridden by the external voltage and by the hysteresis, therefore: v th2(ext)(rise) = (1 + r1/r2) x (v bridge + v hys(ext) /2) v th2(ext)(fall) = (1 + r1/r2) x (v bridge - vhys(ext) /2) where v bridge = 1.25 v typ. and v hys(ext) = 60 mv typ. - the reset pulse width t w is doubled to approximately 16 ms. input poradj is biased internally with a pull-do wn current source of 4 a which is removed when the voltage on pin poradj exceeds 1 v. this ensures that after detection of the external bridge by the ic during power-on, the input current on pin poradj does not cause inaccuracy of the bridge voltage. the minimum threshold voltage should be higher than 2 v. the maximum threshold voltage may be up to v dd . 5.2.3 application examples the voltage supervisor is used as power-on reset and as supply dropout detection during a card session. supply dropout detection is to ensure that a proper deactivation sequence is followed before the voltage is too low. for the internal voltage supervisor to function, the system microcontroller should operate down to 2.35 v to ensure a proper deactivation sequence. if this is not possible, external resistor values can be chosen to overcome the problem. 5.3 clock circuitry (only on so-28 and tssop-28 packages) the card clock signal (clk) is derived from a clock signal input to pin xtal1 or from a crystal operating at up to 26 mhz connected between pins xtal1 and xtal2. the clock frequency can be f xtal , 1/2 x f xtal , 1/4 x f xtal or 1/8 x f xtal . frequency selection is made via inputs clkdiv1 and clkdiv2 (see ta b l e 2 1 ). table 21. clock frequency selection (1) 1. the status of pins clkdiv1 and clkdiv2 must not be changed simultaneously; a delay of 10 ns minimum between changes is needed. the minimum duration of an y state of clk is eight periods of xtal1. clkdiv1 clkdiv2 f clk 00f xtal /8 01f xtal /4 11f xtal /2 10f xtal
functional description st8024l 18/33 doc id 17709 rev 2 the frequency change is synchronous, which means that during transition no pulse is shorter than 45 % of the smallest period, and that the first and last clock pulses about the instant of change have the correct width. when changing the frequency dynamically, the c hange is effective for only eight periods of xtal1 after the command. the duty factor of f xtal depends on the signal present at pin xtal1. in order to reach a 45 to 55 % duty factor on pin clk, the input signal on pin xtal1 should have a duty factor of 48 to 52 % and transition times of less than 5 % of the input signal period. if a crystal is used, the duty factor on pin clk may be 45 to 55 % depending on the circuit layout and on the crystal characteristics and frequency. in other cases, the duty factor on pin clk is guaranteed between 45 and 55 % of the clock period. the crystal oscillator runs as soon as the ic is powered up. if the crystal oscillator is used, or if the clock pulse on pin xtal1 is permanent, the clock pulse is applied to the card as shown in the activation sequences shown in figure 5 and figure 6 if the signal applied to xtal1 is controlled by the system microcontrolle r, the clock pulse will be applied to the card when it is sent by the system micr ocontroller (after completion of the activation sequence). 5.4 i/o transceivers the three data lines i/o, aux1 and aux2 are identical.the idle state is realized by both i/o and i/ouc lines being pulled high via a 11 k resistor (i/o to v cc and i/ouc to v dd ). pin i/o is referenced to v cc , and pin i/ouc to v dd , thus allowing operation when v cc is not equal to v dd . the first side of the transceiver to receive a falling edge becomes the master. an anti-latch circuit disables the detection of falling edges on the line of the other side, which then becomes a slave. after a time delay t d(edge) , an n transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. when the master side returns to logic 1, a p transistor on the slave side is turned on during the time delay t pu and then both sides return to their idle states. this active pull-up feature ensures fast low-to-high transitions; it is able to deliver more than 1 ma at an output voltage of up to 0.9 v cc into an 80 pf load. at the end of the active pull-up pulse, the output voltage depends only on the internal pull-up resistor and the load current. the current to and from the card i/o lines is limited internally to 15 ma and the maximum frequency on these lines is 1 mhz. 5.5 inactive mode after a power-on reset, the circuit enters the inactive mode. a minimum number of circuits are active while waiting for the mi crocontroller to start a session: ? all card contacts are inactive (approximately 200 to gnd) ? pins i/ouc, aux1uc and aux2uc are in the high-impedance state (11 k pull-up resistor to v dd ). applies only to so-28 and tssop-28 packages. ? voltage generators are stopped ? xtal oscillator is running ? voltage supervisor is active ? the internal oscillator is running at its low frequency.
st8024l functional description doc id 17709 rev 2 19/33 5.6 activation sequence after power-on and after the internal pulse width delay, the system microcontroller can check the presence of a card using the signals off and cmdvcc as shown in ta bl e 2 2 . if the card is in the reader (this is the case if pres or pres is active), the system microcontroller can start a card session by pulling cmdvcc low. the following sequence then occurs (see figure 6 ): 1. cmdvcc is pulled low and the internal oscilla tor changes to its high frequency (t 0 ). 2. the step-up converter is started (between t 0 and t 1 ). 3. v cc rises from 0 to 5 v (or 1.8 v, 3 v) with a controlled slope (t 2 = t 1 + 1.5 x t) where t is 64 times the period of the inter nal oscillator (approximately 25 s). 4. i/o, aux1 and aux2 are enabled (t 3 = t 1 + 4t) (these were pulled low until this moment). 5. clk is applied to the c3 contact of the card reader (t 4 ). 6. rst is enabled (t 5 = t 1 + 7t). the clock may be applied to the card using the following sequence (see figure 5 ): 1. set rstin high. 2. set cmdvcc low. 3. reset rstin low between t 3 and t 5 ; clk will start at this moment. 4. rst remains low until t 5 , when rst is enabled to be the copy of rstin. 5. after t 5 , rstin has no further affect on clk; this allows a precise count of clk pulses before toggling rst. if the applied clock is not needed, then cmdvcc may be set low with rstin low. in this case, clk will start at t 3 (minimum 200 ns after the transition on i/o), and after t 5 , rstin may be set high in order to obtain an answer to request (atr) from the card. activation should not be performed with rstin held permanently high. table 22. card presence indicator off cmdvcc indication h h card present l h card not present
functional description st8024l 20/33 doc id 17709 rev 2 figure 5. activation sequence using rstin and cmdvcc figure 6. activation sequence at t 3 c s 17740 c s 17750
st8024l functional description doc id 17709 rev 2 21/33 5.7 active mode when the activation sequence is completed, the st8024l will be in its active mode. data are exchanged between the card and the microcontroller via the i/o lines. the st8024l is designed for cards without v pp (the voltage required to program or erase the internal non-volatile memory). 5.8 deactivation sequence when a session is comp leted, the microcontroller sets the cmdvcc line high. the circuit then executes an automatic deactivation se quence by counting the sequencer back and finishing in the inactive mode (see figure 7 ): 1. rst goes low (t 10 ). 2. clk is held low (t 12 = t 10 + 0.5 x t) where t is 64 times the period of the internal oscillator (approxi mately 25 s). 3. i/o, aux1 and aux2 are pulled low (t 13 = t 10 + t). 4. v cc starts to fall towards zero (t 14 = t 10 + 1.5 x t). 5. the deactivation sequence is complete at t de , when v cc reaches its inactive state. 6. all card contacts become low-impedance to gnd; i/ouc, aux1uc and aux2uc remain at v dd (pulled-up via a 11 k resistor). 7. the internal o scillator returns to its lower frequency. figure 7. deactivation sequence c s 17760
functional description st8024l 22/33 doc id 17709 rev 2 5.9 v cc generator the v cc generator has a capacity to supply up to 80 ma (max) continuously at 5 v, 65 ma (max) at 3 v, and 55 ma (max) at 1.8 v. an internal overload detector operates at approximately 120 ma. current samples to the detector are internally filtered, allowing spurious current pulses up to 200 ma with a duration in the order of s to be drawn by the card without causing deactivation. the average current must stay below the specified maximum current value. for reasons of v cc voltage accuracy, a 100 nf capacitor with an esr < 100 m should be tied to cgnd near to pin v cc , and 100 nf capacitor with the same esr should be tied to cgnd near card reader contact c1. 5.10 fault detection the following fault conditions are monitored: ? short-circuit or high current on v cc ? removal of a card during a transaction ?v dd dropping ? step-up converter operating out of the specified values (v ddp too low or current from v up too high) ?overheating ? there are two different cases (see figure 8 ): ?cmdvcc high outside a card session. output off is low if a card is not in the card reader, and high if a card is in the reader. a voltage drop on the v dd supply is detected by the supply supervisor, this generates an internal power-on reset pulse but does not act upon off . no short-circuit or overheating is detected because the card is not powered-up. ?cmdvcc low within a card session. output off goes low when a fault condition is detected. as soon as this occurs, an emergency deactivation is performed automatically (see figure 9 ). when the system controller resets cmdvcc to high it may sense the off level again after completing the deactivation sequence. this distinguishes between a hardware problem or a card extraction (off goes high again if a card is present). depending on the type of card-present switch within the connector (normally closed or normally open) and on the mechanical characteristics of the switch, bouncing may occur on the pres signals at card insertion or withdrawal. there is a debounce feature in the device with an 8 ms typical duration (see figure 8 ). when a card is inserted, output off goes high only at the end of the debounce time. when the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on pres or pres and output off goes low.
st8024l functional description doc id 17709 rev 2 23/33 figure 8. behavior of off , cmdvcc , pres and v cc figure 9. emergency deactivation sequence (card extraction) c s 177 8 0 c s 17770
functional description st8024l 24/33 doc id 17709 rev 2 5.11 v cc selection settings the st8024l supports three smartcard v cc voltages: 1.8 v, 3 v and 5 v. the v cc selection is controlled by the 1.8v and 5v/3v signals as shown in ta b l e 2 3 . the 1.8v signal has priority over the 5v/3v . when the 1.8v pin is taken high, v cc is 1.8v and it overrides any setting on the 5v/3v pin. when the 1.8v pin is taken low, the 5v/3v pin selects the 5 v or 3 v v cc . if the 5v/3v pin is taken high, then v cc is 5 v and if the 5v/3v pin is taken low then v cc is 3 v. table 23. v cc selection settings 5v/3v pin 1.8v pin v cc output 00 3 v 10 5 v x 1 1.8 v
st8024l applications doc id 17709 rev 2 25/33 6 applications figure 10. hardware hookup 1. these capacitors must be of the low esr-type and be placed near the ic (within 100 mm). 2. st8024l and the microcontroller must use the same v dd supply. 3. make short, straight connections between cgnd, c5 and the ground connection to the capacitor. 4. mount one low esr-type 100 nf capacitor close to pin v cc . 5. mount one low esr-type 100 nf c apacitor close to c1 contact. 6. the connection to c3 should be routed as far from c2 , c7, c4 and c8 and, if possible, surrounded by grounded tracks. 7. this is the optional resistor br idge for changing the threshold of v dd when using the poradj func tion. if this bridge is not required, pin 18 shoul d be connected to ground. clkdiv2 c1? v up pre s pre s i/o aux1 pgnd c1 + v ddp aux2 cgnd 1 2 3 4 5 6 7 8 9 10 11 12 1 3 5 1 4 1 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 clkdiv1 5/ 3 v clk i/ouc xtal2 xtal1 gnd v dd r s tin aux1uc aux2uc v cc r s t off cmdvcc 100k + 3 . 3 v +5v 100nf 100nf 100nf (5) c1 c2 c 3 c4 c5 c6 c7 c 8 k1 k2 100nf 100nf 100nf 10 f 33 pf + 3 . 3 v + 3 . 3 v powered microcontroller card reader (norm a lly clo s ed type) (4) ( 3 ) (6) s t 8 024l + (1) (1) (2) + 3 . 3 v am049 3 0v1 v dd r2 r1 (7) poradj/1. 8 v
package mechanical data st8024l 26/33 doc id 17709 rev 2 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 11. so-28 small outline, package mechanical drawing table 24. so-28 small outline, package mechanical data dimension mm inches min typ max min typ max a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ) d 17.70 18.10 0.697 0.713 e 10.00 10.65 0.393 0.419 e1.27 0.050 e3 16.51 0.650 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s 8 (max) 0016572_f
st8024l package mechanical data doc id 17709 rev 2 27/33 figure 12. tssop-20 package mechanical drawing table 25. tssop-20 package mechanical data dimension mm inches min typ max min typ max a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 c e b a2 a e1 d 1 pin 1 identification a1 l k e 00 8 7225_d
package mechanical data st8024l 28/33 doc id 17709 rev 2 figure 13. tssop-28 package mechanical drawing table 26. tssop-28 package mechanical data dimension mm inches min typ max min typ max a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 9.6 9.7 9.8 0.378 0.382 0.386 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 012 8 292_d
st8024l package mechanical data doc id 17709 rev 2 29/33 figure 14. so-28 tape and reel schematic table 27. so-28 tape and reel mechanical data dimension mm inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n60 2.362 t30.41.197 a o 10.8 11.0 0.425 0.433 b o 18.2 18.4 0.716 0.724 k o 2.9 3.1 0.114 0.122 p o 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 note: dr a wing not to s c a le
package mechanical data st8024l 30/33 doc id 17709 rev 2 figure 15. tssop-20 tape and reel schematic table 28. tssop-20 tape and reel mechanical data dimension mm inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n60 2.362 t22.40.882 a o 6.8 7 0.268 0.276 b o 6.9 7.1 0.272 0.280 k o 1.7 1.9 0.067 0.075 p o 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 note: dr a wing not to s c a le
st8024l package mechanical data doc id 17709 rev 2 31/33 figure 16. tssop-28 tape and reel schematic table 29. tssop-28 tape and reel mechanical data dimension mm inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n60 2.362 t22.40.882 a o 6.8 7 0.268 0.276 b o 10.1 10.3 0.398 0.406 k o 1.7 1.9 0.067 0.075 p o 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 note: dr a wing not to s c a le
revision history st8024l 32/33 doc id 17709 rev 2 8 revision history table 30. document revision history date revision changes 19-jul-2010 1 initial release. 30-jul-2010 2 updated description , ta bl e 6 .
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